Multicell development news

Multicell development news – 05.09.2018


A complete set of software tools for the design and development of applications has been developed. The set includes: C-compiler, assembler, linker and software model (simulator) of multicellular processor Multicell S1. The tools have been tested in the development of processor test programs and CoreMark program (synthetic benchmark to assess the optimal compilation and processor performance). We started the development of test programs for evaluating the performance of the processor when calculating Ethereum hashes.


To achieve the declared performance characteristics of the processor, we performed a deep optimization of RTL code of multicellular – the basic element of the computing cluster. Based on results of the topological synthesis of a finalized multicellular option, under normal conditions, its performance matches the plan. This will ensure, taking into account the processing time of the received data, the maximum possible bandwidth of access paths to external memory, which is critical in the implementation of Ethereum algorithms and, as a consequence, a significant increase in the efficiency of these algorithms compared to hardware analogues. We are testing finalized multicellular option on a debug kit using FPGA Virtex-6. A logical synthesis of a cluster consisting of 4 multicellulars has been carried out and its optimization has been started. We received all the documentation for IP blocks (peripheral blocks PCI-E, DDR4, PLL) and their integration with the previously developed system bus AXI. Is working to deploy a debug position in FPGA Stratix 10 (the complex of SARGON).

In General, the goal of the first stage is reached, allowing to proceed to the execution of works of the second stage in the development of a GDSII file of the project of the microprocessor as a whole.