Interim results of the development of a new generation miner – Multiclet!

Processor MultiCell Ѕ1 consists of 4 clusters, united by the AXI tire. Each cluster includes 4 cores, each of which, in turn, consists of 4 cells. The cell is a processor device, the command system of which is focused on the performance of computational tasks. All cells are identical.


To store and access large amounts of data, two DDR4 controllers (including the physical layer) are connected to the tire, and a PCIe controller (also with the physical layer) on 4 lines is connected to communicate with the external environment.


Hardware. Currently, the cluster code has been developed and tested on RTL tests. We performed a logic synthesis test (28 nm) for a preliminary estimation of the parameters of footprint and performance. We conducted a trial of topological synthesis with the use of no-sheet, obtained during the synthesis . A pre-floorplan of a processor was created. The results of the synthesis confirm the reachability of the declared performance parameters (1.5 GHz) and area by the cluster. In order to reduce the time of testing the CPU in full (using the models of IP blocks supplied with the blocks), we conduct testing of the interaction of cluster and tire using FPGA Xilinx (V6) tools.


Software. We developed assembler and linker which are put into operation and are used at writing of tests of the processor. To debug assembler and C programs, a program model of the processor is created and included in the Geany debugging environment. An alpha version of the compiler has been developed and its trial operation on test sets (CoreMark, etc.) has been started to evaluate the performance.

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